| MRC |
Requirement Statement |
Characteristics |
| CBBL |
FEATURES PROVIDED |
MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS AND W/TOTEM POLE OUTPUT AND HIGH SPEED |
| CQWX |
OUTPUT LOGIC FORM |
TRANSISTOR-TRANSISTOR LOGIC |
| CQZP |
INPUT CIRCUIT PATTERN |
TRIPLE 3 INPUT |
| CQSZ |
INCLOSURE CONFIGURATION |
DUAL-IN-LINE |
| ADAQ |
BODY LENGTH |
0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |
| ADAT |
BODY WIDTH |
0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| AEHX |
MAXIMUM POWER DISSIPATION RATING |
22.0 MILLIWATTS |
| AFGA |
OPERATING TEMP RANGE |
-55.0 TO 125.0 DEG CELSIUS |
| CQSJ |
INCLOSURE MATERIAL |
CERAMIC AND GLASS |
| CSSL |
DESIGN FUNCTION AND QUANTITY |
3 GATE, AND |
| AFJQ |
STORAGE TEMP RANGE |
-65.0 TO 150.0 DEG CELSIUS |
| ADAU |
BODY HEIGHT |
0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| TEST |
TEST DATA DOCUMENT |
95750-17007105 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| CTFT |
CASE OUTLINE SOURCE AND DESIGNATOR |
T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| CZEQ |
TIME RATING PER CHACTERISTIC |
15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 12.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
